1. Field of the Invention
This invention relates to integrated circuit level translators, and more particularly to CMOS to ECL output level translators.
2. Description of Related Art
BiCMOS integrated circuits are suitable for applications requiring higher levels of performance than effectively achieved by traditional CMOS integrated circuits. For example, gate arrays incorporate BiCMOS buffers/drivers to maintain the density advantage of CMOS technology while providing the high drive capacity of bipolar technology. The BiCMOS technology allows designers to create fast ECL input/output ("I/O") circuits and high performance CMOS interfaces.
An example of a CMOS to ECL translator 100 is illustrated in FIG. 1. Transistors 112 and 114 are P-channel and N-channel CMOS transistors respectively, the gates of which share a common CMOS input 116. The drains of transistors 112 and 114 are connected to one another and to the base of an NPN transistor 122, which forms one typical branch of an ECL current switch 120. The other branch of the ECL current switch 120 is formed by NPN transistors 124 and 126, which have shorted collector-base junctions. The two branches of the ECL current switch 120 are connected to V.sub.CC 118 through respective resistors 123 and 127, and are connected to V.sub.EE through a current source 128. The level translator 100 is described in more detail in Alvarez, A.R., BiCMOS Technology and Applications, Kluwer Academic Publishers, Boston, 1989, page 218. The output 130, which is taken from the shorted collector-base of transistor 126, generally is applied to an emitter follower such as 140. A similar translator using an emitter follower driven by a reference voltage VCSB instead of the current source 128 is described in Gallia, James D. et al., "High-performance BiCMOS 100K-gate array," IEEE Journal of Solid State Circuits, Vol. 25, No. 1, February 1990, pp. 142-49.
For applications requiring a normal buffer, the low level on output line 130 is about minus 0.9 volts, which results in about minus 1.7 volts on the emitter of the bipolar buffer transistor 142. In other words, the buffer transistor 142 is never off, but instead is swing controlled. For bus driver applications requiring a cutoff buffer, the transistor 142 should be off when line 130 is low. In such applications, the value of impedance 152 of the bus 150 typically is fifty ohms, and the value of resistor 127 is chosen to ensure that the transistor 142 is off. A suitable output voltage on line 130 under these circumstances would be about minus 1.5 volts, for example.
Unfortunately, the power consumption of the CMOS to ECL translator of FIG. 1 is on the order of conventional ECL buffers. This level of power consumption is inconvenient for ECL LSI integrated circuits, and is excessive for BiCMOS VLSI integrated circuits.